95% off Digital IC Design Using System-Verilog / Verilog (Coupon)

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Digital IC Design Using System-Verilog / Verilog - Udemy Coupon

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Coupon & course info

Course Name: Digital IC Design Using System-Verilog / Verilog

Subtitle: Learn RTL coding in Verilog or System -Veriog with one-to-one mapping between digital circuits and RTL programs.

Instructor: Taught by Ajith Jose, Hardware Engineer

Category: IT & Software

Subcategory: Hardware

Provided by: Udemy

Price: $16 (before discount)

Free coupon code: See above (no charge for coupon)

Review info & popularity

As of March 15, 2016…

Students: 9900 students enrolled

Ratings: 15 reviews

Rank: ranked #339 in Udemy IT & Software Courses

Brief course description

This course teaches the digital IC and ASIC design techniques used in VLSI industry using System Verilog language. It covers the basics of digital design techniques and teaches the basic concepts of using a hardware description language like System Verilog (SV) for IC design.

This course contains video lectures of 1 hour 45 minutes duration. It is stared by explaining a brief history of ICs and evolution of hardware description languages. The starting point learning System Verilog, “writing the first module” is explained here next. The remaining sessions of this course teaches you the SV language constructs, types of modelling and some illustrative examples. Implementation of sequential and combination digital circuits are explained in detail which will help the learner to grab the difficult ideas in using ‘assign’ & ‘always’ and ‘blocking’& ‘non-blocking assignments’ in SV.

By taking this course, the a student will be able to start digital design using Verilog or System Verilog and master it slowly. This course will also be helpful for the SV programmers who know how to write an SV program but not clear about how they actually get implemented to a hardware.

(Read more about this course on the official course page.)

Ajith Jose bio

A post graduate in electronics engineering with several years of industrial experience in ASIC design and Verification using System Verilog at major semiconductor companies. A passionate and continuous learner in emerging technologies in VSLI and also interested in other technical domains related to programming. Finds energy in learning new technologies and and sharing knowledge with others.

(Learn more about this instructor on the official course page.)

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Final details for this Udemy course

Languages: English

Skill level: Beginner Level

Lectures: 14 lessons

Duration: 2 Hours of video

What you get: Write System-Verilog RTL programs for designing ASICs and Digital ICs

Target audience: This System-Verilog course will be an ideal starting point towards learning RTL coding for Digital ICs and ASICs. The intended audience are students and professionals who are NOT experts in Verilog or System-Verilog IC design

Requirements: There are no prerequisites for this course but it is good to know basics of Digital circuits and programming in any language.

Access: Lifetime access

Peace of mind: 30 day money back guarantee

Availability: available online, as well as on iOS and Android

Download options: check course to see if you can download lessons

95% off SystemVerilog Verification -2: Object Oriented Programming (Coupon)

Attention: This post may contain affiliate links, meaning when you click the links and make a purchase, we receive a commission at no extra cost to you. Thanks!

SystemVerilog Verification -2: Object Oriented Programming - Udemy Coupon

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Bonus: download a free guide that reveals 11 tricks for getting the biggest discounts on Udemy courses, including this course.

Coupon & course info

Course Name: SystemVerilog Verification -2: Object Oriented Programming

Subtitle: System Verilog : Master the concepts of Object Oriented Programming (OOPs) in System Verilog to build reusable TBs.

Instructor: Taught by Ajith Jose, Hardware Engineer

Category: IT & Software

Subcategory: Hardware

Provided by: Udemy

Price: $40 (before discount)

Free coupon code: See above (no charge for coupon)

Review info & popularity

As of July 11, 2016…

Students: 905 students enrolled

Ratings: 23 reviews

Rank: ranked #143a in Udemy IT & Software Courses

Brief course description

This course teaches the SystemVerilog language used in the VLSI industry for System-On-Chip design verification. This is primarily focusing on the Object Oriented Programming (OOPs / OOP) concepts of SystemVerilog.

This course contains video lectures of 2.2 hours duration. It is stared by explaining what is Object Oriented Programming and how it is used for TB writing. It explains the concepts of using array and structures in any programming language and comes to the idea of using in classes thereafter. The definition, creation and usage of objects are described in detail.

Below is the summary of the topics covered in this course

(Read more about this course on the official course page.)

Ajith Jose bio

A post graduate in electronics engineering with 8+ years of industrial experience in ASIC design and Verification using System Verilog at major semiconductor companies. A passionate and continuous learner in emerging technologies in VSLI and also interested in other technical domains related to programming. Finds energy in learning new technologies and and sharing knowledge with others.

(Learn more about this instructor on the official course page.)

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Final details for this Udemy course

Languages: English

Skill level: Intermediate Level

Lectures: 18 lessons

Duration: 1.5 hours of video

What you get: Understand the concepts of Object Oriented Progrmming

Target audience: This is a SystemVerilog verification course ideal for those who know the basics of SV and want to master it by using the wonderful features of OOPs in their verification programs. This course is probably not for you if you clearly know the OOPS concepts and familiar with System Verilog.

Requirements: You need to be familiar with the basics of SystemVerilog Programming and Test Bench writing.

Access: Lifetime access

Peace of mind: 30 day money back guarantee

Availability: available online, as well as on iOS and Android

Download options: check course to see if you can download lessons

95% off SystemVerilog Verification -3 : Build Your Random TestBench (Coupon)

Attention: This post may contain affiliate links, meaning when you click the links and make a purchase, we receive a commission at no extra cost to you. Thanks!

SystemVerilog Verification -3 : Build Your Random TestBench - Udemy Coupon

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Bonus: download a free guide that reveals 11 tricks for getting the biggest discounts on Udemy courses, including this course.

Coupon & course info

Course Name: SystemVerilog Verification -3 : Build Your Random TestBench

Subtitle: System Verilog : Learn the Constraint Random Verification features in SV to build a Random TestBech for SoC Verification

Instructor: Taught by Ajith Jose, Hardware Engineer

Category: IT & Software

Subcategory: Hardware

Provided by: Udemy

Price: $20 (before discount)

Free coupon code: See above (no charge for coupon)

Review info & popularity

As of September 8, 2016…

Students: 1060 students enrolled

Ratings: 11 reviews

Rank: ranked #184d in Udemy IT & Software Courses

Brief course description

This course teaches the SystemVerilog language used in the VLSI industry for System-On-Chip design verification. This is primarily focusing on the reusable random testing features of SystemVerilog.

This course contains video lectures of 2 hours duration. It is stared by explaining what is Constraint Random Verification (CRV) and how it can be implemented in a SV TestBench. It explains the concepts of using random variables in a class and how to add different types of constraints to to them. Below summary of the topics covered in this course.

By taking this course, the you will be able to start using CRV support features in SystemVerilog for effective TestBench coding. This course will an excellent platform to grab the magical features of SystemVerilog to build reusable random who understand the basic of it.

(Read more about this course on the official course page.)

Ajith Jose bio

A post graduate in electronics engineering with 8+ years of industrial experience in ASIC design and Verification using System Verilog at major semiconductor companies. A passionate and continuous learner in emerging technologies in VSLI and also interested in other technical domains related to programming. Finds energy in learning new technologies and and sharing knowledge with others.

(Learn more about this instructor on the official course page.)

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Final details for this Udemy course

Languages: English

Skill level: Intermediate Level

Lectures: 22 lessons

Duration: 1.5 hours of video

What you get: Understand the concepts of Constraint Roandom Verification in System Verilog

Target audience: This is a SystemVerilog verification course ideal for those who know the basics of SV and want to build effective random TestBench for SoC verification. This course is probably not for you if you know clearly the CRV features in System Verilog and a master in writing random TB

Requirements: You need to be familiar with the basics of SystemVerilog Programming and Object Oriented Programming in SV

Access: Lifetime access

Peace of mind: 30 day money back guarantee

Availability: available online, as well as on iOS and Android

Download options: check course to see if you can download lessons

95% off SystemVerilog Design-1: Start Programming Your Own IC in HDL (Coupon)

Attention: This post may contain affiliate links, meaning when you click the links and make a purchase, we receive a commission at no extra cost to you. Thanks!

SystemVerilog Design-1: Start Programming Your Own IC in HDL - Udemy Coupon

Get Discount


Bonus: download a free guide that reveals 11 tricks for getting the biggest discounts on Udemy courses, including this course.

Coupon & course info

Course Name: SystemVerilog Design-1: Start Programming Your Own IC in HDL

Subtitle: VLSI : Learn Verilog / System Verilog for SOC Design – Map digital circuits to HDL programs & begin RTL coding

Instructor: Taught by Hardware Engineer

Category: IT & Software

Subcategory: Hardware

Provided by: Udemy

Price: $99.99 (before discount)

Free coupon code: See above (no charge for coupon)

Review info & popularity

As of March 15, 2019…

Students: 1540 students enrolled

Ratings: 191 reviews

Rank: ranked #808 in Udemy IT & Software Courses

Brief course description

This System Verilog course teaches the digital IC and ASIC design techniques used in VLSI industry. It covers the basics of digital design techniques and teaches the basic concepts of using a hardware description language like System Verilog (SV) for IC design.

This course contains video lectures of 1 hour 45 minutes duration. It is stared by explaining a brief history of ICs and evolution of hardware description languages. The starting point learning System Verilog, “writing the first module” is explained here next. The remaining sessions of this course teaches you the SV language constructs, types of modelling and some illustrative examples. Implementation of sequential and combination digital circuits are explained in detail which will help the learner to grab the difficult ideas in using ‘assign’ & ‘always’ and ‘blocking’& ‘non-blocking assignments’ in SV.

By taking this course, the a student will be able to start digital design using Verilog or System Verilog and master it slowly. This course will also be helpful for the SV programmers who know how to write an SV program but not clear about how they actually get implemented to a hardware.

(Read more about this course on the official course page.)

Ajith Jose bio

A post graduate in electronics engineering with over 10 years of experience in ASIC design & verification with major semiconductor companies like Intel India and ARM UK.  An expert in Systemverilog for design & verification coding, and Universal Verification Methodology (UVM)  as well. A passionate and continuous learner in emerging technologies in VLSI.

(Learn more about this instructor on the official course page.)

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Final details for this Udemy course

Languages: English

Skill level: N/A

Lectures: 16 lectures lessons

Duration: 2 hours of video

What you get: Write System-Verilog RTL programs for designing ASICs and Digital ICs

Target audience: This System-Verilog course will be an ideal starting point towards learning RTL coding for Digital ICs and ASICs. The intended audience are students and professionals who are NOT experts in Verilog or System-Verilog IC design

Requirements: There are no prerequisites for this course but it is good to know basics of Digital circuits and programming in any language.

Access: Lifetime access

Peace of mind: 30 day money back guarantee

Availability: available online, as well as on iOS and Android

Download options: check course to see if you can download lessons