Coupon & course info
Course Name: Learn to build OVM & UVM Testbenches from scratch
Subtitle: Learn and Start building Verification Testbenches in SystemVerilog based Verification Methodologies – OVM and UVM
Instructor: Taught by Ramdas Mozhikunnath M, Expert Verification Engineer, Intel Alumni, 16+ years exp
Category: IT & Software
Subcategory: Hardware
Provided by: Udemy
Price: $19 (before discount)
Free coupon code: See above (no charge for coupon)
Review info & popularity
As of March 15, 2016…
Students: 88880 students enrolled
Ratings: 19 reviews
Rank: ranked #468 in Udemy IT & Software Courses
Brief course description
The Verification industry is adopting SystemVerilog based UVM Methodology at a rapid pace for most of the current ASIC/SOC Designs and is considered as a key skill for any job in the front end VLSI design/verification jobs.
This course teaches
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(Read more about this course on the official course page.)
Ramdas Mozhikunnath M bio
Expert and Passionate Verification Engineer with 16+ years of experience in design verification of complex Microprocessors, ASIC and SOC designs at major semiconductor companies like Intel, IBM and other exciting startups. Passionate in continuous learning of new and interesting technologies and always ready to share knowledge and help others
(Learn more about this instructor on the official course page.)
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Final details for this Udemy course
Languages: English
Skill level: All Levels
Lectures: 36 lessons
Duration: 5.5 Hours of video
What you get: Understand concepts behind OVM and UVM Verification methodologies
Target audience: Verification engineers who have basic understanding of SystemVerilog but new to OVM/UVM methodology
Requirements: Basic understanding of Functional Verification concepts
Access: Lifetime access
Peace of mind: 30 day money back guarantee
Availability: available online, as well as on iOS and Android
Download options: check course to see if you can download lessons