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SystemVerilog Verification -2: Object Oriented Programming - Udemy Coupon

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Coupon & course info

Course Name: SystemVerilog Verification -2: Object Oriented Programming

Subtitle: System Verilog : Master the concepts of Object Oriented Programming (OOPs) in System Verilog to build reusable TBs.

Instructor: Taught by Ajith Jose, Hardware Engineer

Category: IT & Software

Subcategory: Hardware

Provided by: Udemy

Price: $40 (before discount)

Free coupon code: See above (no charge for coupon)

Review info & popularity

As of July 11, 2016…

Students: 905 students enrolled

Ratings: 23 reviews

Rank: ranked #143a in Udemy IT & Software Courses

Brief course description

This course teaches the SystemVerilog language used in the VLSI industry for System-On-Chip design verification. This is primarily focusing on the Object Oriented Programming (OOPs / OOP) concepts of SystemVerilog.

This course contains video lectures of 2.2 hours duration. It is stared by explaining what is Object Oriented Programming and how it is used for TB writing. It explains the concepts of using array and structures in any programming language and comes to the idea of using in classes thereafter. The definition, creation and usage of objects are described in detail.

Below is the summary of the topics covered in this course

(Read more about this course on the official course page.)

Ajith Jose bio

A post graduate in electronics engineering with 8+ years of industrial experience in ASIC design and Verification using System Verilog at major semiconductor companies. A passionate and continuous learner in emerging technologies in VSLI and also interested in other technical domains related to programming. Finds energy in learning new technologies and and sharing knowledge with others.

(Learn more about this instructor on the official course page.)

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Final details for this Udemy course

Languages: English

Skill level: Intermediate Level

Lectures: 18 lessons

Duration: 1.5 hours of video

What you get: Understand the concepts of Object Oriented Progrmming

Target audience: This is a SystemVerilog verification course ideal for those who know the basics of SV and want to master it by using the wonderful features of OOPs in their verification programs. This course is probably not for you if you clearly know the OOPS concepts and familiar with System Verilog.

Requirements: You need to be familiar with the basics of SystemVerilog Programming and Test Bench writing.

Access: Lifetime access

Peace of mind: 30 day money back guarantee

Availability: available online, as well as on iOS and Android

Download options: check course to see if you can download lessons